Method for shielding logic signals

ABSTRACT

A method for routing conductors in an integrated circuit design is disclosed, including the steps of determining the number of sensitive conductors requiring placement into quiet track locations, wherein a quiet track location is defined as any track location immediately adjacent to a stable conductor, determining the number of quiet track locations available in said integrated circuit design, and routing one or more sensitive conductors into one or more quiet track locations.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to electronic systems utilizinglogic signals. More particularly, the present invention provides amethod for shielding signal lines which would otherwise inductively orcapacitively couple to adjacent conductors.

[0003] 2. The Background Art

[0004] As integrated circuit (IC) designs become more complex, and asthose designs utilize higher signal frequencies, there is an increasedlikelihood of crosstalk between adjacent interconnect lines within oneor more functional blocks in an IC.

[0005] Typical IC's include large and small functional blocks coupledtogether by interconnect lines.

[0006]FIG. 1 is a block diagram of a prior art IC showing megablocks andinterconnect lines.

[0007] Referring to FIG. 1, integrated circuit 10 comprises megablocks12, 14, 16, 18, and 20, each megablock being connected to othermegablocks by interconnect lines 22 a through 22 i provided for thatpurpose. Each of megablocks 12, 14, 16, 18, and 20 includes logic gates,transistors, and other components. It is common for IC's to includemegablocks which have rows of functional circuits, with the circuitrywithin one or more rows being connected to circuitry in other rows byinterconnects which are located in tracks. A track is a location on anintegrated circuit die in which an interconnect may be placed, dependingon a given design.

[0008]FIG. 2 depicts a typical layout of a prior art megablock showingpower, ground, and possible track locations.

[0009] Referring to FIG. 2, megablock 30 comprises power conductors 32 athrough 32 h provided therein to supply power to columns of bit slices36 a through 36 h, and ground conductors 34 a through 34 h. In a typicalmegablock, each row such as rows 38 and 40 might have similar functionalcircuitry throughout each of the bit slices, with the functionalcircuitry in a given bit slice being connected to circuitry in adifferent row.

[0010]FIG. 3 depicts a prior art bit slice in any given row within amegablock.

[0011] Referring to FIG. 3, bit slice 40 comprises power conductor 42,ground conductor 44, dotted lines showing potential track locations 46,48, and 50, and conductors 52 and 54. In a typical bit slice, there aremany more signal paths which connect various functional blocks togetherin order to perform the intended function. However, only two signalpaths are depicted herein in order to avoid needlessly overcomplicatingthe disclosure and drawings.

[0012] As circuit designs become more complex, and utilize higher andhigher signal frequencies, the distance between conductors becomes anincreasingly critical factor due to the possibility that signals on oneconductors might be inductively or capacitively coupled to one or moreother conductors. For example, conductor 52 is adjacent to conductor 54,making it possible that a signal on conductor 54 might beunintentionally coupled to conductor 52, causing conductor 52 to act ina way which is not intended by the designer.

[0013] In order to understand how the prior art routes conductors sothat unintended coupling between conductors is minimized, it isnecessary to understand how integrated circuits are designed.

[0014] Typically, circuitry functionality is modeled in a high-levellanguage such as Verilog. The model is then provided to an analyzerwhich determines the placement of functional blocks and the routing ofcircuitry, so that the intended design functions as modeled. Thus,although the designer determines the input and output conditionsnecessary for proper functionality of a system, the placement ofconductors such as conductors 52 and 54 in a single bit slice such asdepicted in FIG. 2 is determined using design rules. These design rulesinclude details specifically associated with the manufacturing processwhich will be used to manufacture the IC.

[0015] One element of a design which is controllable, and which alsoaffects the placement of conductors in a bit slice is whether a givensignal path requires a “quiet” environment in which to operate. If agiven signal path is required to be placed in an environment whereinductive and capacitive coupling is minimized, the designer providesthat information in the model supplied to the analyzer, and the analyzertakes appropriate action to maximize the coupling of the sensitiveconductor to a constant signal source. The appropriate prior art actionis to add a new conductor.

[0016] For example, in FIG. 4, sensitive conductor 52 has been placed bythe analyzer in the location depicted, immediately adjacent to noisyconductor 54. In order to minimize the coupling between conductor 52 andconductor 54, prior art analyzers route a third conductor 60 from astable conductor, such as ground conductor 44, to a position adjacent toconductor 52.

[0017] This technique for routing a constant conductor is known to thoseof ordinary skill in the art to cause a sensitive conductor to partiallycouple to the constant conductor, thus minimizing the coupling of thesensitive conductor to the noisy conductor. However, this technique alsomandates the use of an available track within a bit slice for theplacement of the extra conductor, making the use of that track for othercircuitry impossible. In order to provide enough silicon real estate toaccomplish this technique in crowded bit slices, it is often necessaryto design the wafer to allow for larger bit slices, an undesirableeffect.

[0018] While the methods used in the prior art are effective forminimizing the inductive and capacitive coupling of noisy signal pathsto sensitive signal paths, prior art methods suffer in that significantunnecessary use of silicon real estate results from those methods.

[0019] It would therefore be beneficial to provide a method forminimizing coupling of noisy conductors to sensitive conductors whichutilizes less silicon real estate than the prior art.

SUMMARY OF THE INVENTION

[0020] A method for routing conductors in an integrated circuit designis disclosed, including the steps of determining the number of sensitiveconductors requiring placement into quiet track locations, wherein aquiet track location is defined as any track location immediatelyadjacent to a stable conductor, determining the number of quiet tracklocations available in said integrated circuit design, and routing oneor more sensitive conductors into one or more quiet track locations.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 is a block diagram of a prior art IC showing megablocks andinterconnect lines.

[0022]FIG. 2 depicts a typical layout of a prior art megablock showingpower, ground, and possible track locations.

[0023]FIG. 3 depicts a prior art bit slice in any given row within amegablock.

[0024]FIG. 4 depicts the prior art bit slice of FIG. 3 further includinga quieting conductor.

[0025]FIG. 5 depicts a present invention bit slice having conductorsrouted according to one embodiment of the present invention.

[0026]FIG. 6 is a side view of a bit slice of an integrated circuitshowing preferred tracks for the placement of sensitive conductors.

[0027]FIG. 7 is a flow chart showing steps in a method of the presentinvention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

[0028] Those of ordinary skill in the art will realize that thefollowing description of the present invention is illustrative only andnot way any way limiting. Other embodiments of the invention willreadily suggest themselves to such skilled persons.

[0029] In this disclosure, a stable conductor shall generally refer to aconductor which does not change state. The examples used in thisdisclosure of stable conductors are power and ground. However, those ofordinary skill in the art will readily recognize that other stableconductors fitting this description exist in the art.

[0030]FIG. 5 depicts a bit slice having conductors routed according toone embodiment of the present invention.

[0031] Referring to FIG. 5, noisy conductor 54 is placed as previouslyseen in FIG. 3. However, conductor 62, a conductor determined to becritically sensitive, has been placed immediately adjacent to stableground conductor 44. Noisy conductor 64 although adjacent to conductor62 does not inductively couple to conductor 62 due to the “quieting”influence on conductor 62 by ground conductor 44.

[0032] Because integrated circuits are constructed using multiple metallayers, the quieting influence on a conductor by a stable conductor isnot restricted to a single metal layer. Therefore, so long as asensitive conductor needing a quiet environment is designed to be placedat a track location immediately adjacent to a stable conductor, theeffects of the quieting influence of the stable conductor may be felt.

[0033]FIG. 6 is a side view of a bit slice of an integrated circuitshowing preferred tracks for the placement of sensitive conductors.

[0034] Referring to FIG. 6, bit slice 70 includes two metal layers 72and 74, with each of layers 72 and 74 including a power conductor 42 anda ground conductor 44. According to one embodiment of the presentinvention, “quiet” locations for the placement of sensitive conductorsinclude tracks 76 a through 76 h. These tracks are all immediatelyadjacent to stable conductors.

[0035] Tracks such as track 76 a, which are immediately adjacent to morethan one stable conductor, are considered to be especially quiet, due tothe increased coupling to more than one stable conductor. Therefore,tracks 76 a, 76 c, 76 f and 76 g are especially quiet, and should beutilized for placement of the most sensitive conductors, as determinedby the IC designer. An IC may have four or more metal layers, providingfor potential quiet tracks above, below, left, and right of a givenstable conductor.

[0036]FIG. 7 is a flow chart showing steps in a method according to thepresent invention.

[0037] Referring to FIG. 7, the method begins at step 80 wherein thesignal conductors which need a quiet environment in which to operate areprioritized. At this step, if a given design is known to have fewersensitive lines than preferred tracks to place them, all sensitiveconductors may be routed into a preferred location. Alternatively, adesigner may rank each sensitive conductor in order of its importancerelative to other sensitive conductors. In this alternative case,conductors are routed according to their rank, thus ensuring that themore highly ranked conductors are placed in quiet track locations.

[0038] At step 82, It is determined how many preferred tracks exist inthe present design. At this step, the analyzer may alternatively rankthe preferred tracks, ranking the tracks which are immediately adjacentto two stable conductors higher than tracks which are immediatelyadjacent to a single stable conductor.

[0039] At step 84, the analyzer routes sensitive conductors into trackspreviously designated at step 82. If, at step 80, the designer hadranked sensitive conductors according to the desirability of placingthem in a stable location, the analyzer routes the higher rankedconductors first. If, at step 82, the analyzer had ranked the preferredtracks according to whether any given preferred track had one, two, ormore adjacent stable conductors, the analyzer, at step 84, places themost highly ranked sensitive conductor at the most preferred location.The analyzer then places the next highest ranked sensitive conductor atthe next most preferred track location, and so on, until all rankedconductors have been placed.

[0040] At step 86, the analyzer routes any conductors not already routedinto the remaining track locations.

[0041] While embodiments and applications of this invention have beenshown and described, it would be apparent to those skilled in the artthat many more modifications than mentioned above are possible withoutdeparting from the inventive concepts herein. The invention, therefore,is not to be restricted except in the spirit of the appended claims.

What is claimed is:
 1. A method for routing conductors in an integratedcircuit design comprising the steps of: determining the number ofsensitive conductors requiring placement into quiet track locations,wherein a quiet track location is defined as any track locationimmediately adjacent to a stable conductor; determining the number ofquiet track locations available in said integrated circuit design;routing one or more sensitive conductors into one or more quiet tracklocations.
 2. The method of claim 1 further comprising the step of:ranking one or more sensitive conductors according to the relativedesirability of said one or more sensitive conductors being placed intoa quiet environment, as compared to other conductors; and wherein saidrouting step further includes the step of routing said ranked sensitiveconductors, according to said ranking.
 3. The method of claim 2 furthercomprising the step of: ranking one or more preferred track locationsaccording to whether said one or more preferred track locations areadjacent to one or more stable conductors; and wherein said routing stepfurther includes the step of routing said ranked sensitive conductors,according to said track location ranking, and said sensitive conductorranking.
 4. A computer system for routing conductors in an integratedcircuit design, the computer system comprising: a processor; and amemory having stored therein the following means for determining thenumber of sensitive conductors requiring placement into a quiet tracklocation, wherein a quiet track location is defined as any tracklocation immediately adjacent to a stable conductor; means fordetermining the number of quiet track locations available in saidintegrated circuit design; means for routing one or more sensitiveconductors into one or more quiet track locations.
 5. The computersystem according to claim 4, the memory further having stored thereinthe following: means for ranking one or more sensitive conductorsaccording to the relative desirability of said one or more sensitiveconductors being placed into a quiet environment, as compared to otherconductors; and means for routing said ranked sensitive conductors,according to said ranking.
 6. The computer system according to claim 4,the memory further having stored therein the following: means forranking one or more preferred track locations according to whether saidone or more preferred track locations are adjacent to one or more stableconductors; and means for routing said ranked sensitive conductors,according to said track location ranking, and said sensitive conductorranking.
 7. A machine-readable medium disposed on a computer to performa method for routing conductors in an integrated circuit design, themethod comprising the steps of: determining the number of sensitiveconductors requiring placement into a quiet track location, wherein aquiet track location is defined as any track location immediatelyadjacent to a stable conductor; determining the number of quiet tracklocations available in said integrated circuit design; routing one ormore sensitive conductors into one or more quiet track locations.
 8. Themachine-readable medium of claim 7, the method therein furthercomprising the step of: ranking one or more sensitive conductorsaccording to the relative desirability of said one or more sensitiveconductors being placed into a quiet environment, as compared to otherconductors; and wherein said routing step further includes the step ofrouting said ranked sensitive conductors, according to said ranking. 9.The machine-readable medium of claim 8, the method therein furthercomprising the step of: ranking one or more preferred track locationsaccording to whether said one or more preferred track locations areadjacent to one or more stable conductors; and wherein said routing stepfurther includes the step of routing said ranked sensitive conductors,according to said track location ranking and said sensitive conductorranking.